\section{Example application HDL entities}
\label{sec:ExampleApp}
The example application, the user application inside the FPGA is a very simple example, implemented in wupper\_oc\_top.vhd. It has two modes of operation, controlled by the LOOPBACK register. 

\begin{enumerate}
	\item LOOPBACK=0: A 64-bit counter increments on every FIFO write into the ToHost memory, this is referred to as "write only" or "half loop" test. 
	\item LOOPBACK=1: The software allocates 2 buffers, then initializes the first buffer with some content. Two DMA operations are then initialized into both directions (ToHost and FromHost) and the two datastreams are connected to each other internally in the firmware example. The result is a copy of the memory into the second buffer, this is referred as "read and write" or "full loop" test.  
\end{enumerate}
